Hybrid Row Architecture Optimization for Sub-3nm Physical Design

As semiconductor technology is moving toward sub-3nm nodes, traditional design approaches are faced with enormous obstacles related to power, performance, and area (PPA) optimization; ensuring low interconnect delays; and integration of devices. Hybrid row architecture allows flexibility and scalability through the use of non-uniform standard cell layouts, heterogeneous devices, and innovative interconnect solutions. In this review, we examine new trends in hybrid row architectures and their potential for making contributions toward interconnect design-technology co-optimization, BEOL scaling, CFET integration, and 3D-IC realization. We also review how hybrid rows fit into the canon of other new design paradigms such as hierarchical graph embedding and machine learning based optimization. This review documents both the architectural advantages and practical implementations of hybrid rows with respect to enabling advanced physical design at sub-micron and likely nanoscale devices while still permitting (and perhaps enabling) integration of plasmonic and photonic devices for next generation computing systems.