AI-Driven Instruction Set Discovery for 64-Bit LoongArch Architecture (AIDIS-LA64)

Artificial intelligence workloads are expanding at a speed that surpasses the evolution of general-purpose CPUs. Traditional instruction-set architecture (ISA) design processes, which rely on slow and expert-driven manual analysis, increasingly struggle to meet the demands of deep learning systems whose computational requirements grow exponentially [13], [29]. This thesis introduces AIDIS-LA64, an automated framework for discovering optimized vector instruction extensions for the 64-bit LoongArch architecture. The framework integrates workload profiling, evolutionary search, multi-objective fitness modeling, and QEMU-based execution validation to generate instructions tailored for neural network inference.

Using a CNN model trained on the MNIST dataset, the system discovered six efficient vector instructions targeting INT8 and FP16 arithmetic, aligned with contemporary low-precision inference strategies [15], [16], [17]. These instructions accelerate convolution, activation, pooling, and normalization operations—representing the majority of CNN computation. The evolutionary process converged rapidly, generating instruction sets that achieved a simulated 369,923× throughput improvement over scalar LoongArch64 code. QEMU-based micro-kernel benchmarking validated expected performance ordering across precision levels, consistent with behavior reported in recent processor simulation research [23], [24].

The results demonstrate that automated ISA discovery can accelerate architecture evolution for AI workloads, reducing human design effort while exploring a broader design space than traditional methods allow. AIDIS-LA64 contributes a replicable methodology for AI-guided CPU instruction design, relevant not only for LoongArch64 but for any emerging or evolving RISC architecture